MSI H6M-P3 (B3) Bedienungsanleitung

February 2004ORDERING NUMBERS: STA013$ (SO28) STA013T$ (TQFP44)

3.1.2 - Stop conditionSTOP is identified by low to high transition of thedata bus SDA signal while the clock signal SCL isstable in the high state. A

3.4 - READ OPERATION (see Fig. 11)3.4.1 - Current byte address readThe STA013 has an internal byte addresscounter. Each time a byte is written or rea

I2C REGISTERS (continued)HEX_COD DEC_COD DESCRIPTION RESET R/W$43 67 HEAD_H[23:16] 0x00 R(8)$44 68 HEAD_M[15:8] 0x00 R(8)$45 69 HEAD_L[7:0] 0x00 R(8)$

4.1 - STA013 REGISTERS DESCRIPTIONThe STA013 device includes 128 I2C registers. Inthis document, only the user-oriented registersare described. The un

Hardware Reset: 0x01The REQ_POL registers is used to program thepolarity of the DATA_REQ line.MSB LSBb7 b6 b5 b4 b3 b2 b1 b000000001Default polarity (

DATA_REQ_ENABLEAddress: 0x18Type: R/WSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0 DescriptionX X X X X 0 X X buffered output

ANCCOUNT_LAddress: 0x41Type: ROSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0ANCCOUNT_HAddress:

The meaning of the flags are shown in the follow-ing tables:MPEG IDsIDex ID0 0 MPEG 2.50 1 reserved1 0 MPEG 21 1 MPEG 1Layer in Layer III these two fl

DLA register is used to attenuate the level ofaudio output at the Left Channel using the butter-fly shown in Fig. 12. When the register is set to255 (

DRAAddress: 0x48Type: R/WSoftware Reset: 0X00Hardware Reset: 0X00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0 DescriptionDRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 OUT

I2C CONTROLSERIALINPUTINTERFACEBUFFERMPEG 2.5LAYER IIIDECODERCORECHANNELCONFIG.&VOLUMECONTROLOUTPUTBUFFERPCMOUTPUTINTERFACEPARSER26 3 4RESETSDA SC

PLLFRAC_441_HAddress: 0x52Type: R/WSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8The regi

PCMCONFAddress: 0x55Type: R/WSoftware Reset: 0x21Hardware Reset: 0x21MSB LSBb7 b6 b5 b4 b3 b2 b1 b0 DescriptionX ORD DIF INV FOR SCL PREC (1) PREC (1)

PCMCROSSAddress: 0x56Type: R/WSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0 DescriptionX X X X X X 0 0 Left channel is mapped

PLLFRAC_L ([7:0])MSB LSBb7 b6 b5 b4 b3 b2 b1 b0PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0PLLFRAC_H ([15:8])MSB LSBb7 b6 b5 b4 b3 b2 b1 b0PF15 PF14 PF13 PF12 PF11

RUNAddress: 0x72Type: RWSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0XXXXXXXRUNSetting this register to 1, STA013 leaves the

TREBLE_ENHANCEAddress: 0x7BSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0Signed number (2 compl

BASS_ENHANCEAddress: 0x7CSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0Signed number (2 complem

TONE_ATTENAddress: 0x7DType: RWSoftware Reset: 0x00Hardware Reset: 0x00MSB LSBb7 b6 b5 b4 b3 b2 b1 b0TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0In the digital out

The Ancillary Data extraction on STA013 can bedescribed as follow:STA013 has a specific Ancillary Data buffer,mapped into the I2C registers:0x59 ANC_D

5.4. TIMING DIAGRAMS5.4.1. Audio DAC Interfacea) OCLK in output. The audio PLL is used to clock the DACOCLK (OUTPUT)SDOSCKTLRCLKtsdotsckttlrclkD98AU96

Figure 2. Pin ConnectionVDD_1VSS_1RESETSDASCLSCKRSDIBIT_ENSDOVDD_4VSS_4XTIFILTXTOPVSSPVDDVDD_3VSS_31324567892625242322202119271028VDD_2TESTEND98AU911A

SDISCKRIGNORED VALIDIGNOREDt_bitent_bitentsdi_holdtsdi_setupD98AU971Atsckr_min_highBIT_ENSCLK_POL=0tsckr_min_lowtsckr_min_period5.4.2. Bitstream input

RESETD98AU974treset_low_min5.4.5. RESETThe Reset min duration (t_reset_low_min) is 100nsHW RESETsetPCM OUTPUTINTERFACECONFIGURATIONsetsetPCM-DIVIDERPC

Table 5:PLL Configuration Sequence For10MHz Input Clock256 Oversapling ClockREGISTERADDRESSNAME VALUE6 reserved 1811 reserved 397 MFSDF (x) 1580 MFSDF

Table 9:PLL Configuration Sequence For14.31818MHz Input Clock512 Oversapling RathioREGISTERADDRESSNAME VALUE6 reserved 1111 reserved 397 MFSDF (x) 680

5.6. STA013 CONFIGURATION FILE FORMATThe STA013 Configuration File is an ASCII format. An example of the file format is the following:58 142 4

SO28DIM.mm inchMIN. TYP. MAX. MIN. TYP. MAX.A 2.65 0.104a1 0.1 0.3 0.004 0.012b 0.35 0.49 0.014 0.019b1 0.23 0.32 0.009 0.013C 0.5 0.020c1 45° (typ.)D

OUTLINE ANDMECHANICAL DATADIM.mm inchMIN. TYP. MAX. MIN. TYP. MAX.A 1.60 0.063A1 0.05 0.15 0.002 0.006A2 1.35 1.40 1.45 0.053 0.055 0.057B 0.30 0.37 0

OUTLINE ANDMECHANICAL DATAD1 DA0.15A1A2effA12345678BCDEFGHE1φ b (64 PLACES)EBALL 1 IDENTIFICATIONLFBGA64MDIM.mm inchMIN. TYP. MAX. MIN. TYP. MAX.A 1.7

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequencesof use of suc

PIN DESCRIPTIONSO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description1 29 B5 VDD_1 Supply Voltage2 30 B4 VSS_1 Ground3 31 A4 SDA I/O i2C Serial Da

1. ELECTRICAL CHARACTERISTICS: VDD = 2.7V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwisespecifiedDC OPERATING CONDITIONSSymbol Parameter ValueVDDP

VDD100nF12VDD100nF1413VSSVDD100nF1615VDD100nF2322VSSVSSVSS17 18272826RESET24TESTEN25SCANENOUT_CLK/DATA_REQVDDPVSSPVDD100nF4.7µF 4.7µFPVDDPVSSVSS10K1K4

SCLK_POL=0SCLK_POL=4DATA IGNOREDDATA VALIDSCKRSCKRSDIBIT_END98AU968ADATA IGNOREDFigure 6. Serial Input Interface ClocksDATASOURCEµPMPEGDECODERIICD9

RCCXTI2DSPCLKXTI2OCLKXSNMPFD CPVCOSwitchingCircuitOCLKDCLKUpdate FRACFRACXTIDisable PLLFigure 7. PLL and Clocks Generation System2.4 - PCM Output Inte

2.5 - STA013 Operation ModeThe STA013 can work in two different modes,called Multimedia Mode and Broadcast Mode.In Multimedia Mode, STA013 decodes the