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Chapter 3

3-14

Current FSB/DRAM Frequency

The fields are used to display current host bus (Front Side Bus)/DRAM

clock frequency.

DRAM Clock

The chipset supports synchronous and asynchronous mode between

host clock and DRAM clock frequency. Available settings are:

Host CLK: The DRAM clock will be equal to the Host clock.

HCLK-33M: The DRAM clock will be equal to the Host clock minus

33MHz. For example, if the Host clock is 133MHz, the

DRAM clock will be 100MHz.

HCLK+33M: The DRAM clock will be equal to the Host clock plus

33MHz. For example, if the Host clock is 100MHz, the

DRAM clock will 133MHz.

By SPD: DRAM clock frequency is determined based on the con-

tents of SPD EEPROM on the DRAM module.

DRAM Timing

The field determines whether DRAM timing is configured by reading

the contents of the SPD (Serial Presence Detect) EEPROM on the DRAM

module. Selecting By SPD makes SDRAM CAS Latency and Bank

Interleave automatically determined by BIOS according to the configu-

rations on the SPD.

SDRAM CAS Latency

The field controls the timing delay before SDRAM starts a read com-

mand after receiving it. Settings: 2.5 and 2 (clock cycles). 2 increases

system performance while 2.5 provides more stable system performance.

Bank Interleave

Select 2- or 4-Bank interleave for installed SDRAM. Settings: 2 Bank, 4

Bank and Disabled.

AGP & P2P Bridge Control

Press <Enter> to go to the sub-menu screen similar to the following.

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MSI MS-9105 Bedienerhandbuch Seite 56